1. Field of the Invention
The present invention relates to a pseudo static RAM (SRAM), and more particularly to a pseudo SRAM and a method for operating the same that can perform a page write mode.
2. Description of the Prior Art
As generally known in the art, a RAM (random access memory) among semiconductor memories is a memory in which random access to any storage is possible and both write and read of information can be performed, and is widely used as a memory of a computer or a peripheral terminal. The RAM has the advantage of low cost, small size, lower power consumption, high-speed call, non-destructive decoding, etc., but has the disadvantage that if a power is gone, all data stored are erased. There are two kinds of RAMs. One is a dynamic RAM that keeps hold of information by a refresh operation at predetermined intervals in a power-on state. The other is a static RAM that keeps hold of information if only the power is on.
A memory that loses information if the power is off is called a volatile memory, while a memory that does not lose information even if the power is off such as a ROM (read only memory) is called a non-volatile memory. The static RAM has the advantage that it can be easily connected to other integrated circuits, but requires three or four times as many as the number of elements of the dynamic RAM for the same storage capacity, so that its construction is complicated with a high cost in comparison to the dynamic RAM.
Currently, researches for a so-called pseudo SRAM that implements the same operation as the static RAM using cells of the dynamic RAM have actively been in progress. The pseudo static RAM has the advantage that its chip size is reduced in comparison to existing SRAMs to achieve a high-level integration of 16 Mbits, 32 Mbits, 64 Mbits, etc. However, since the cell of the pseudo SRAM has the same structure as those of the dynamic RAM, the refresh operation should be performed therein.
The memory technology has been developed with two brief purposes. One is to heighten the degree of integration and to provide a mass storage device. The other is to improve the speed of data read from a memory and/or of data write into the memory. The pseudo SRAM that implements the operation of the SRAM using the cells of the dynamic RAM originates in efforts for storing larger-capacity data than the existing SRAM, but the present invention is derived from efforts for performing a write operation at a higher speed than the existing pseudo SRAM.
Up to the present, the pseudo SRAM can perform only a signal write mode for writing data only in a column after activating on a row, but cannot perform a so-called page write mode for continuously writing data in many column without an intermediate pre-charge operation. FIG. 1 is a timing diagram illustrating the operation of the conventional pseudo SRAM that performs the single write mode. In FIG. 1, waveforms of external signals are shown. xe2x80x98/CSxe2x80x99 denotes a chip select signal, xe2x80x98A0xcx9cAmxe2x80x99 a column address signal, xe2x80x98Am+1xcx9cAnxe2x80x9d a row address signal, xe2x80x98/WExe2x80x99 a write enable signal, xe2x80x98/LBxe2x80x99 and xe2x80x98/UBxe2x80x99 are lower and upper block control signals, xe2x80x98DINxe2x80x99 a data signal inputted to the pseudo SRAM, and xe2x80x98DOUTxe2x80x99 a data signal outputted from the SRAM, respectively. In a typical pseudo SRAM, there is no distinction between the column address signal and the external address signal. For convenience"" sake in explanation, they will be explained in distinction from each other.
In FIG. 1, the AC characteristics of the conventional pseudo SRAM are also defined. In FIG. 1, xe2x80x98tWCxe2x80x99 denotes a time required from a chip select to a write end, xe2x80x98tWCxe2x80x99 a write cycle time, and xe2x80x98tAWxe2x80x99 a time required from reception of an effective address signal to a write end. Also, xe2x80x98tASxe2x80x99 denotes an address setup time, xe2x80x98tWPxe2x80x99 a write pulse width, xe2x80x98tWRxe2x80x99 a write restoration time, and xe2x80x98tBWxe2x80x99 a time required from reception of an effective block control signal to a write end. Also, xe2x80x98tDWxe2x80x99 denotes a time required from a data reception to a write end, xe2x80x98tDHxe2x80x99 a data hold time in a write operation, xe2x80x98tWHZxe2x80x99 a time when high impedance is outputted from a write start, and xe2x80x98tOWxe2x80x99 is a time required from a write end to output activation. A shaded portion in the chip select signal /CS and the block control signals /LB and /UB represents a don""t care signal, and an oblique-line portion in the output data signal DOUT represents invalid data. Also, xe2x80x98H-Zxe2x80x99 in the input data DIN and in the output data DOUT represents a high-impedance state.
As shown in FIG. 1, in the conventional single write mode, since the write operation is performed with respect to only one column according to row activation for once, it is difficult to perform a high-speed write operation. That is, according to the existing single write mode, in which for each write command, the row activation is performed and data is written in cells of the corresponding column, the row activation is performed again even if the same address as the row address previously activated is continuously inputted, and thus the high-speed write operation cannot be performed. Accordingly, it is necessary to implement a page write mode in which the write operation is continuously performed with respect to several columns corresponding to a previously set page width among the corresponding columns by one row-activation operation.
However, as described above, since the pseudo SRAM uses the cells of the dynamic RAM, the refresh should be performed at predetermined intervals, and at the same time since the pseudo SRAM operates in the same manner as other SRAMs, it should send and receive a command signal, data signal, address signal, etc., in the same manner (i.e., protocol) as other SRAMs. In the single write mode, the refresh does not matter in particular since the time required for the write operation is not so long, but in the page write mode, the write operation should be performed for a long time without an intermediate refresh operation, and thus data may be lost during the page write mode in the pseudo SRAM using the dynamic RAM. Accordingly, in order to perform the page write mode in the pseudo SRAM, it is essential to properly perform the refresh operation in relation to the page write operation.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a pseudo SRAM that can implement a page write mode even using cells of dynamic RAM.
Another object of the present invention is to provide a method of performing a page write mode in a pseudo SRAM using cells of a dynamic RAM.
In order to accomplish this object, there is provided a pseudo SRAM having a new structure. The pseudo SRAM according to the present invention performs a page write according to a specified edge of a write command signal in a state that a word line is continuously activated without an intermediate pre-charge after one row activation in a column address corresponding to a predetermined page width. Then, the pseudo SRAM internally performs a self-refresh according to its characteristics. If a refresh request signal precedes a write command, it terminates the refresh, and if the pre-charge signal is generated, it performs a write operation. To prepare for the worst, it makes the minimum value of tCW, tWC, tAW, and tBW larger than the sum of a refresh cycle time and a single write cycle time. If the refresh request time follows the write command, it terminates the write mode by releasing the chip select, and if the pre-charge signal is generated, it performs the refresh operation. Also, since the cell data may be lost if the page write is performed for a long time and thus the internal refresh cannot be performed, it keeps a period in which the chip is not selected as long as a read cycle time (hereinafter, referred to as xe2x80x9ctRCxe2x80x9d) so that the refresh can be performed in the middle of the write operation if the page-write time is longer than a refresh time period tREF. The refresh time period tREF is a time period obtained by dividing the whole retention time by the whole number of rows. According to the present invention, the write operation in the pseudo SRAM can be performed at a high speed.
In one aspect of the present invention, there is provided a pseudo SRAM that includes a memory cell array composed of cells of a dynamic RAM, a buffer enable block for receiving an external chip select signal and generating a buffer enable signal and an internal chip select signal, and a write enable signal buffer section for receiving an external write enable signal and generating a write command signal. The pseudo SRAM is also provided with a page width setup section for generating a page width select signal according to a set page width, a refresh control section for performing a refresh of the memory cell array by generating a refresh request signal at predetermined refresh intervals, and a page address strobe signal generating section for generating a page address strobe signal in case that the write command signal has a specified transition at a pre-chargeable time point after a row activation of the cell array. The pseudo SRAM is also provided with a data buffer section for receiving an external data signal if the buffer enable signal is received and generating an internal data signal, an address buffer section for receiving an external address signal if the buffer enable signal is received and generating an internal address signal, latching the internal address signal according to the page address strobe signal, and generating no address transition detection signal if the generated internal address signal is within the page width according to the page width select signal, while generating an address transition detection signal if the generated internal address signal is outside the page width, an input/output control section for receiving the internal address signal, the internal data signal, the write command signal, the internal chip select signal, the refresh request signal, and the page width select signal, the input/output control section, if the internal address signal corresponds to the page width according to the page width select signal, controlling the refresh control section so that the refresh operation is not performed as keeping the specified row activation state of the memory cell array activated by the previous address signal, and performing a page write operation for writing the internal data signal in columns of the memory cell array corresponding to the internal address signal according to the transition of the write command signal, and a pre-charge control section for pre-charging the input/output control section if the address transition detection signal is received.
In another aspect of the present invention, there is provided a method of performing a method of performing a page write mode in a pseudo SRAM having a memory cell array composed of cells of a dynamic RAM, comprising a first step of first performing a refresh operation of the memory cell array, and then performing a write operation if generation of a refresh request signal precedes generation of a write command signal, and a second step of first performing the write operation of the memory cell array, and then performing the refresh operation if the generation of the write command signal precedes the generation of the refresh request signal.
The write operation may includes a first substep of first writing one-bit data in a corresponding cell after performing activation of a specified row of the memory cell array by the write command signal, a second substep of writing the data in the cell corresponding to a next address signal as keeping the activation state of the activated row if a next address signal received from the outside is within a predetermined page width, and a third substep of writing the corresponding data by activating the row of the memory cell array corresponding to the next address after performing the refresh operation of the memory cell array if the next address is outside the page width. It is determined that a time required for the first substep is larger than a sum of a refresh cycle time and a single write cycle time. The second substep is continuously performed only for a time smaller than the refresh period.